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Building for Tomorrow: Design Considerations for 224G System Architecture 

224 Gbps-PAM4 technology presents significant opportunities for advancing hyperscale data centers, promising a substantial increase in data transmission speeds from 112 Gbps to 224 Gbps. But while the major leap from 112G to 224G will enable new capabilities in AI, high-performance computing and beyond, the blistering speeds introduce unique challenges. 

Read Time: 6 Min

Pushing the limits of engineering and manufacturing, the successful development and deployment of a 224G-based system demands a complete system architecture overhaul, leaving designers and implementers to determine the best path forward. How do we ensure optimal signal integrity? And what can we do about the increasing amount of heat dissipation associated with these systems? These questions and more are at the core of our exploration into the design considerations for building a robust, reliable 224 Gbps-PAM4 system architecture.

Signal Integrity

Because of its unprecedented high-speed transmission, deploying 224 Gbps-PAM4 technology introduces an array of signal integrity hurdles. The technology’s reliance on higher frequencies and complex modulation schemes makes it sensitive to transmission loss, insertion loss, crosstalk, reflection and jitter — all potentially causing signal degradation and compromised network performance. Here are some of the essential factors for preserving signal integrity within 224G data center architectures.

Shielding, Grounding and Layout

The electromagnetic interference (EMI) generated by adjacent high-speed signals (aggressors) can disrupt nearby signals (victims), impacting transmission reliability. This becomes particularly challenging with the high frequencies of 224G systems. To mitigate crosstalk, it’s crucial to create shielding between the signal lines by designing proper enclosures, implementing conductive ground planes and ground lines, and using shielded wiring solutions. 

Effective grounding allows unwanted currents to move away, preventing them from interfering with signal paths. Careful layout planning and early provisioning of ground traces are crucial for reducing crosstalk risks at high frequencies. These techniques ensure uninterrupted signal transmission at high frequencies, which is essential for maintaining signal integrity.

Precise Component Placement and Material Selection

In 224G system architecture, every detail matters. Every component, from PCBs and cables to connectors and chips, must be carefully selected for its low-loss characteristics to mitigate signal attenuation and distortions. Trace lengths — the physical distance an electrical signal travels on a PCB — need precise control and matched routing to synchronize signals across intricate PCB layouts. Manufacturing tolerances also need to be much tighter for such systems, as the system behavior and noise in the transmitted signals can be easily distorted by poor manufacturing of the components, mismatched soldering and out-of-specification dimensions.

Power Delivery and Thermal Management

Along with the arrival of 224G technology comes greater power requirements and more significant thermal management concerns. What are some ways to address these challenges?

Solving for Higher Power Requirements

224 Gbps-PAM4 transceivers and equipment consume significantly more power than previous generations. A data center’s power infrastructure needs to be able to handle this increased load. System architects should invest in upgraded Power Distribution Units (PDUs) with both higher capacity and redundancy to avoid bottlenecks. Design engineers should use low-loss, high-efficiency cabling to minimize power losses. Additionally, 224G systems should deploy dynamic power management (DPM) systems that can adjust power allocation based on real-time demands. Effective DPM will help reduce the system’s energy consumption, improve thermal management by reducing heat dissipation and increase overall system performance. When it comes to input power delivery, every electrical system has a certain tolerance for abnormalities around the nominal target values. The 224G systems are more sensitive to the quality of the input power, and as such, extra attention should be given to reducing noise, overshoot, droop, and jitter in the input power.  

Developing Needed Thermal Management Strategies

High-speed data transmissions generate a substantial amount of heat. If the generated heat is not removed effectively from the system components, the components may exceed their allowable temperature limits or experience temperature fluctuations. As a result, the heat will impact component performance and can cause permanent physical damage to the hardware. Because of this, thermal management must be a high priority when designing for 224G systems and beyond.

Efficient cooling systems are key to the safe, reliable and efficient operation of data centers. As an example of an industry-wide effort, the Open Compute Project (OCP) Cooling Environments project has assembled teams of industry experts to develop best-known practices and standards for efficient cooling of data centers and their components. 224G system hardware performance is especially sensitive to high temperature values. As such, thermal design engineers should optimize the airflow in the system for efficient heat transfer from these systems and maintain the temperature of critical components below their recommended reliable operating limits. The temperature of components and the thermal state of the system should be monitored continuously to identify and address thermal issues and hotspots before they become problematic. 

Power delivery and thermal management are interconnected, and the strategies described above help mitigate both challenges.

Low Latency

224G applications need to receive critical information almost instantaneously. Even the slightest delay can negatively affect sensitive applications like autonomous vehicles, remote surgery and industrial automation processes. It’s important to minimize — or even eliminate latency — every step of the way. Any unbalanced or unintentional delays in the system and transmission lines could significantly impact the system performance and transmission line behavior.  

Fewer Stops, Less Latency

Instead of routing through multiple switches or routers, system architects should prioritize direct connections between devices whenever possible. Each hop through a network node adds to overall latency. Minimizing packet processing steps also reduces latency. The fewer stops a packet makes, the more efficiently it moves through the system. Furthermore, fewer stops reduce the risk of unbalanced delay due to design deficiencies or manufacturing tolerances. Intelligent traffic management and efficient routing protocols keep packets moving swiftly to their destination.

Optimized Network Hardware

Choosing the right components for efficient dataflow has a significant effect on latency. System architectures should include high-quality connectors designed and optimized specifically for 224G speeds. Efficient switches and routers specifically designed for low-latency operation will minimize processing delays between network devices. These components include features like cut-through switching, hardware offloading and low buffer latency. They have also been manufactured with state-of-the-art techniques and have been tested thoroughly for functionality and performance. 

Standards and Scalability

Design engineers also must futureproof their high-speed data center system architecture. In order to do so, they need to follow standards and think in terms of scalability. Following established standards also helps to reduce the system’s overall cost by using widely available components and by leveraging high volumes of such systems. These approaches support robustness and reliability of the supply chain to ensure on-time delivery.  

Emerging Standards for Higher Bandwidths

For the highest speeds and scalability, OSFP (Octal Small Form Factor Pluggable) and QSFP-DD have emerged as a prominent open-source standard for pluggable transceivers used in data centers. Both modules can support speeds of up to 800 Gbps and feature high signal integrity and cool 25-30W power consumption. QSFP-DD (Quad Small Form-Factor Pluggable Double-Density) and OSFP transceivers present a high-performance option for data centers, doubling the density of their predecessors, enabling high transfer speeds and futureproofing data centers for even higher bandwidth demands. Both QSFP-DD and OSFP are widely accepted standards for data center transceivers and have attracted both significant industry support and widespread adoption.

Related Products: OSFP 112 Gbps PAM-4 Interconnect System and Cable Assemblies, QSFP-DD Connector System 

Collaborating for Flexibility

High-speed data centers require architectures that adapt and readily expand. Modular and scalable approaches simplify these challenges. Independent, replaceable modules — like compute nodes and network switches — enable swapping or adding blocks as needs evolve. This flexibility is one of the hallmarks of the Open Compute Project (OCP), a collaborative effort of industry leaders, among which Molex is an active participant.

Emphasizing this modular, scalable approach, OCP’s work reflects a keen understanding of the challenges and opportunities presented in creating system infrastructures that will be able to seamlessly integrate with future data center technologies.

A Cross-Functional Design Approach

Molex’s unique co-development approach keeps collaboration at the core of innovation. By bringing together system architects, hardware specialists and semiconductor experts, Molex works with customers to co-develop tailored data center solutions. Molex offers a comprehensive range of high-performance data center products, designed specifically for 224G architectures. Through collaboration from the beginning of the design process, Molex helps customers realize the tremendous potential of 224G data centers.

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